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1 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* 16m-bit [2m x 8/1m x 16] cmos single voltage flash eeprom advanced information ? status register feature for detection of program or erase cycle completion ? low vcc write inhibit is equal to or less than 1.8v ? software data protection ? page program operation - internal address and data latches for 64 words per page - page programming time: 5ms typical ? low power dissipation - 50ma active current - 20ua standby current ? two independently protected sectors ? package type - 42 pin plastic dip * for page mode read only general description the mx29l1611g is a 16-mega bit flash memory organized as either 1m wordx16 or 2m bytex8. the mx29l1611g includes 32 sectors of 64kb(65,536 bytes or 32,768 words). mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx29l1611g is packaged in 42 pin pdip. the standard mx29l1611g offers access times as fast as 100ns,allowing operation of high-speed microprocessors without wait. to eliminate bus contention, the mx29l1611g has separate chip enable ce and, output enable (oe). mxic's flash memories augment eprom functionality with electrical erasure and programming. the mx29l1611g uses a command register to manage this functionality. mx29l1611g does require high input voltages for programming. commands require 11v input to determine the operation of the device. reading data out of the device is similar to reading from an eprom. mxic flash technology reliably stores memory contents even after 100 cycles. the mxic's cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29l1611g uses a 11v vpp supply to perform the auto erase and auto program algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc +1v. features ? 3.3v 10% for write and read operation ? 11v vpp erase/programming operation ? endurance: 100 cycles ? fast random access time: 90ns/100ns/120ns ? fast page access time: 30ns (only for 29l1611pc-90/ 10/12) ? sector erase architecture - 32 equal sectors of 64k bytes each - sector erase time: 200ms typical ? auto erase and auto program algorithms - automatically erases any one of the sectors or the whole chip - automatically programs and verifies data at specified addresses
2 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* pin configurations 42 pdip pin description symbol pin name a0 - a19 address input q0 - q14 data input/output q15/a-1 q15(word mode)/lsb addr.(byte mode, for read mode only) ce chip enable input oe output enable input byte/vpp word/byte selection input, erase/ program supply voltage vcc power supply gnd ground pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte/vpp gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc mx29l1611g
3 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* block diagram control input logic program/erase high voltage write s tat e machine (wsm) command interface register (cir) mx29l1611g flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier y-select q0-q15/a-1 q15/a-1 a0-a19 ce oe byte / vpp
4 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* table1. pin descriptions symbol type name and function a0 - a19 input address inputs: for memory addresses. addresses are internally latched during a write cycle. q0 - q7 input/output low-byte data bus: input data and commands during command interface register(cir) write cycles. outputs array,status and identifier data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. q8 - q14 input/output high-byte data bus: inputs data during x 16 data-write operations. outputs array, identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected or the outputs are disabled q15/a -1 input/output selects between high-byte data input/output(byte = high) and lsb address(byte = low) for raed operation. ce input chip enable inputs: activate the device's control logic, input buffers, decoders and sense amplifiers. with ce high, the device is deselected and power consumption reduces to standby level upon completion of any current program or erase operations. ce must be low to select the device. oe input output enables: gates the device's data through the output buffers during a read cycle oe is active low. byte/vpp input byte enable: while operating read mode, byte low places device in x8 mode. all data is then input or output on q0-7 and q8-14 float. addressq15/ a-1 selects between the high and low byte. while operating read mode, byte high places the device in x16 mode, and turns off the q15/a-1 input buffer. address a0, then becomes the lowest order address. erase/program enable:when byte/vpp=11v would place this device into erase/program mode. vcc device power supply(3.3v 10%) gnd ground
5 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* table2.2 bus operations for byte-wide mode (byte = vil) mode n otes ce oe byte/vpp a0 a1 a9 q0-q7 q8-q14 q15/a-1 read 1 vil vil vil x x x dout highz vil/vih output disable 1 vil vih vil x x x high z high z x standby 1 vih x h/l x x x high z high z x manufacturer id 2,4 vil vil vil vil vil vid c2h high z vil device id 2,4 vil vil vil vih vil vid f6h high z vil write 1,3,5 vil vih vpp x x x din din din table 2.1 bus operations for word-wide mode (byte/vpp = vih) mode n otes ce oe byte/vpp a0 a1 a9 q0-q7 q8-q14 q15/a-1 read 1 vil vil vih x x x dout dout dout output disable 1 vil vih vih x x x high z high z highz standby 1 vih x h/l x x x high z high z highz manufacturer id 2,4 vil vil vih vil vil vid c2h 00h 0b device id 2,4 vil vil vih vih vil vid f6h 00h 0b write 1,3,5 vil vih vpp x x x din din din bus operation flash memory reads, erases and writes in-system via the local cpu . all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. notes : 1. x can be vih or vil for address or control pins. 2. a0 and a1 at vil provide manufacturer id codes. a0 at vih and a1 at vil provide device id codes. a0 at vil, a1 at vih and with appropriate sector addresses provide sector protect code.(refer to table 4),a2~a19=do not care. 3. commands for different erase operations, data program operations or sector protect operations can only be successfully completed through proper command sequence. 4. vid = 11.5v- 12.5v 5. word mode only for write operation vpp=10.5v~11.5v
6 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* table 3. command definitions(byte/vpp=vhh) command read/ silicon page chip sector read clear sequence reset id read program erase erase status reg. status reg. bus write 4 4 4 6 6 4 3 cycles req'd first bus addr 5555h 5555h 5555h 5555h 5555h 5555h 5555h write cycle data aah aah aah aah aah aah aah second bus addr 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah 2aaah write cycle data 55h 55h 55h 55h 55h 55h 55h third bus addr 5555h 5555h 5555h 5555h 5555h 5555h 5555h write cycle data f0h 90h a0h 80h 80h 70h 50h fourth bus addr ra 00h/01h pa 5555h 5555h x read/write cycle data rd c2h/f6h pd aah aah srd fifth bus addr 2aaah 2aaah write cycle data 55h 55h sixth bus addr 5555h sa write cycle data 10h 30h write operations commands are written to the command interface register (cir) using standard microprocessor write timings. the cir serves as the interface between the microprocessor and the internal chip operation. the cir can decipher read array, read silicon id, erase and program command. in the event of a read command, the cir simply points the read path at either the array or the silicon id, depending on the specific read command given. for a program or erase cycle, the cir informs the write state machine that a program or erase has been requested. during a program cycle, the write state machine will control the program sequences and the cir will only respond to status reads. during a sector/chip erase cycle, the cir will respond to status reads. after the write state machine has completed its task, it will allow the cir to respond to its full command set. the cir stays at read status register mode until the microprocessor issues another valid command sequence. device operations are selected by writing commands into the cir. table 3 below defines 16 mbit flash family command.
7 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* notes: 1. address bit a15 -- a19 = x = don't care for all address commands except for program address(pa) and sector address(sa). 5555h and 2aaah address command codes stand for hex number starting from a0 to a14. 2. bus operations are defined in table 2. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the ce pulse. sa = address of the sector to be erased. the combination of a15 -- a19 will uniquely select any sector. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of ce. srd = data read from status register. 5. only q0-q7 command data is taken, q8-q15 = don't care. * refer to table 4, figure 11. ** only the top and the bottom sectors have protect- bit feature. sa = (a19,a18,a17,a16,a15) = 00000b or 11111b is valid. table 3. command definitions command sector sector verify sector abort sequence protection unprotect protect bus write 6 6 4 3 cycles req'd first bus addr 5555h 5555h 5555h 5555h write cycle data aah aah aah aah second bus addr 2aaah 2aaah 2aaah 2aaah write cycle data 55h 55h 55h 55h third bus addr 5555h 5555h 5555h 5555h write cycle data 60h 60h 90h e0h fourth bus addr 5555h 5555h sa** read/write cycle data aah aah c2h* fifth bus addr 2aaah 2aaah write cycle data 55h 55h sixth bus addr sa** sa** write cycle data 20h 40h
8 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* table 4. mx29l1611g silion id codes and verify sector protect code type a 19 a 18 a 17 a 16 a 15 a 1 a 0 code(hex) q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 manufacturer code x x x x x vil vil c2h* 1 1 0 0 0 0 1 0 mx29l1611g device code x x x x x vil vih f6h* 1 1 1 1 0 1 1 0 verify sector protect sector address*** vih vil c2h** 1 1 0 0 0 0 1 0 * mx29l1611g manufacturer code = c2h, device code = f6h when byte/vpp = vil mx29l1611g manufacturer code = 00c2h, device code = 00f6h when byte/vpp = vih ** outputs c2h at protected sector address, 00h at unprotected scetor address. ***only the top and the bottom sectors have protect-bit feature. sector address = (a19, a18,a17,a16,a15) = 00000b or 11111b device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force vid (11.5v~12.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from vil to vih. all addresses are don't cares except a0 and a1. the manufacturer and device codes may also be read via the command register, for instances when the mx29l1611g is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 3. byte 0 (a0=vil) represents the manfacturer's code (mxic=c2h) and byte 1 (a0=vih) the device identifier code (mx29l1611g=f6h). to terminate the operation, it is necessary to write the read/reset command sequence into the cir.
9 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the cir contents are altered by a valid command sequence. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required for "read operation". standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. the mx29l1611g is accessed like an eprom. when ce and oe are low the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual line control gives designers flexibility in preventing bus contention. note that the read/reset command is not valid when program or erase is in progress. page read the mx29l1611g offers "fast page mode read" function. the users can take the access time advantage if keeping ce, oe at low and the same page address (a3~a19 unchanged). please refer to figure 5-2 for detailed timing waveform. the system performance could be enhanced by initiating 1 normal read and 7 fast page reads(for word mode a0~a2) or 15 fast page reads(for byte mode altering a-1~a2). page program the device is set up in the programming mode when vpp=11v is applied oe=vih. to initiate page program mode, a three-cycle command sequence is required. there are two "unlock" write cycles. these are followed by writing the page program command-a0h. any attempt to write to the device without the three-cycle command sequence will not start the internal write state machine(wsm), no data will be written to the device. after three-cycle command sequence is given, a byte(word) load is performed by applying a low pulse on the ce input with ce low and oe high. the address is latched on the falling edge of ce. the data is latched by the first rising edge of ce. maximum of 64 words of data may be loaded into each page by the same procedure as outlined in the page program section below. program any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. the device is programmed on a page basis. if a word of data within a page is to be changed, data for the entire page can be loaded into the device. any word that is not loaded during the programming of its page will be still in the erased state (i.e. ffh). once the words of a page are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data word has been loaded into the device, successive words are entered in the same manner. each new word to be programmed must have its high to low transition on ce within 30us of the low to high transition of ce of the preceding word. a6 to a19 specify the page address, i.e., the device is page-aligned on 64 words boundary. the page address must be valid during each high to low transition of ce. a0 to a5 specify the word address withih the page. the word may be loaded in any order; sequential loading is not required. if a high to low transition of ce is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. the auto page program terminates when status on q7 is '1' at which time the device stays at read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 1,7,8) chip erase the device is set up in the erase mode when vpp=11v is applied oe=vih. chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the
10 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* sector erase sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command-80h. two more "unlock" write cycles are then followed by the sector erase command-30h. the sector address is latched on the falling edge of ce, while the command (data) is latched on the rising edge of ce. sector erase does not require the user to program the device prior to erase. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins on the rising edge of the last ce pulse in the command sequence and terminates when the status on q7 is "1" at which time the device stays at read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 3,4,6,8) a19 a18 a17 a16 a15 address range [a19, -1] sa0 0 0 0 0 0 000000h--00ffffh sa1 0 0 0 0 1 010000h--01ffffh sa2 0 0 0 1 0 020000h--02ffffh sa3 0 0 0 1 1 030000h--03ffffh sa4 0 0 1 0 0 040000h--04ffffh ... ... ... ... ... ................................ sa31 1 1 1 1 1 1f0000h--1fffffh table 5. mx29l1611g sector address table (byte-wide mode) read status register the mxic's 16 mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the cir. after writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the cir. a read array command must be written to the cir to return to the read array mode. the status register bits are output on q3 - q7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the mx29l1611g. in the word-wide mode the upper byte, q(8:15) is set to 00h during a read status command. in the byte-wide mode, q(8:14) are tri-stated and q15/a-1 retains the low order address function. it should be noted that the contents of the status register are latched on the falling edge of oe or ce whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce or oe must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. the status register is the interface between the microprocessor and the write state machine (wsm). when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. the wsm sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. if erase fail or program fail status bit is detected, the status register is not cleared until the clear status register command is written. the mx29l1611g automatically outputs status register data when read after chip erase, sector erase, page program or read status command write cycle. the default state of the status register after powerup and return from deep power-down mode is (q7, q6, q5, q4) = 1000b. q3 = 0 or 1 depends on sector-protect status, can not be changed by clear status register command or write state machine. "set-up" command-80h. two more "unlock" write cycles are then followed by the chip erase command-10h. chip erase does not require the user to program the device prior to erase. the automatic erase begins on the rising edge of the last ce pulse in the command sequence and terminates when the status on q7 is "1" at which time the device stays at read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence.(refer to table 3,6 and figure 2,6,8)
11 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* clear status register the eraes fail status bit (q5) and program fail status bit (q4) are set by the write state machine, and can only be reset by the system software. these bits can indicate various failure conditions(see table 6). by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). the status register may then be read to determine if an error occurred during that programming or erasure series. this adds flexibility to the way the device may be programmed or erased. additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. the program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. to clear the status register, the clear status register command is written to the cir. then, any other command may be issued to the cir. note again that before a read cycle can be initiated, a read command must be written to the cir to specify whether the read data is to come from the array, status register or silicon id.
12 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* table 6. mx29l1611g status register status notes q7 q6 q5 q4 q3 in progress program 1,2,5 0 0 0 0 0/1 erase 1,3,5 0 0 0 0 0/1 complete program 1,2,5 1 0 0 0 0/1 erase 1,3,5 1 0 0 0 0/1 fail program 1,4,5 1 0 0 1 0/1 erase 1,4,5 1 0 1 0 0/1 after clearing status register 5 1 0 0 0 0/1 notes: 1. q7 : write state machine status 1 = ready, 0 = busy q5 : erase fail status 1 = fail in erase, 0 = successful erase q4 : program fail status 1 = fail in program, 0 = successful program q3 : sector-protect status 1 = sector 0 or/and 15 protected 0 = none of sector protected q6,q2 - 0 = reserved for future enhancements. these bits are reserved for future use ; mask them out when polling the status register. 2. program status is for the status during page programming or sector unprotect mode. 3. erase status is for the status during sector/chip erase or sector protection mode. 4. fail status bit(q4 or q5) is provided during page program or sector/chip erase modes respectively. 5. q3 = 0 or1 depends on sector-protect status.
13 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence. abort mode to activate abort mode, a three-bus cycle operation is required. the e0h command (refer to table 3) only stops page program or sector /chip erase operation currently in progress and puts the device in abort mode. so the program or erase operation will not be completed. since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (q4) or erase fail (q5)bit will be set. a read array command must be written to bring the device out of the abort state without incurring any wake up latency. note that once device is brought out, clear status register mode is required before a program or erase operation can be executed. sector protection to activate this mode, a six-bus cycle operation and vpp=11v are required. there are two 'unlock' write cycles. these are followed by writing the 'set-up' command. two more 'unlock' write cycles are then followed by the lock sector command - 20h. sector address is latched on the falling edge of ce of the sixth cycle of the command sequence. the automatic lock operation begins on the rising edge of the last ce pulse in the command sequence and terminates when the status on q7 is '1' at which time the device stays at the read status register mode. the device remains enabled for read status register mode until the cir contents are altered by a valid command sequence (refer to table 3,6 and figure 9,11). verify sector protect to verify the protect status of the top and the bottom sector, operation is initiated by writing silicon id read command into the command register. following the command write, a read cycle from address xx00h retrieves the manufacturer code of c2h. a read cycle from xx01h returns the device code f8h. a read cycle from appropriate address returns information as to which sectors are protected. to terminate the operation, it is necessary to write the read/reset command sequence into the cir. (refer to table 3,4 and figure 11) a few retries are required if protect status can not be verified successfully after each operation. sector unprotect it is also possible to unprotect the sector , same as the first five write command cycles in activating sector protection mode followed by the unprotect sector command -40h, the automatic unprotect operation begins on the rising edge of the last ce pulse in the command sequence and terminates when the status on dq7 is '1' at which time the device stays at the read status register mode. (refer to table 3,6 and figure 10,11) data protection the mx29l1611g is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read array mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transitions or system noise.
14 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* low vcc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for vcc less than vlko(typically 1.8v). if vcc < vlko, the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the vcc level is greater than vlko. it is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when vcc is above vlko. write pulse "glitch" protection noise pulses of less than 10ns (typical) on ce will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil,ce = vih. to initiate a write cycle, ce must be a logical zero while oe is a logical one, and vpp=11v should be applied.
15 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 1. automatic page program flow chart start write data a0h address 5555h no write data 55h address 2aaah write data aah address 5555h byte/vpp=vhh loading end? page program completed yes yes no sr7 = 1 ? wait 100us read status register write program data/address sr4 = 0 ? program error yes no yes to continue other operations, do clear s.r. mode first program another page? operation done, device stays at read s.r. mode note : s.r. stands for status register no byte/vpp=vih/vil
16 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 2. automatic chip erase flow chart start write data 80h address 5555h no write data 55h address 2aaah byte/vpp=vhh chip erase completed yes yes no sr7 = 1 ? write data aah address 5555h read status register sr5 = 0 ? erase error write data aah address 5555h write data 55h address 2aaah write data 10h address 5555h byte/vpp=vih/vil operation done, device stays at read s.r. mode to continue other operations, do clear s.r. mode first
17 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 3. automatic sector erase flow chart start write data 80h address 5555h no write data 55h address 2aaah byte/vpp=vhh sector erase completed yes yes no sr7 = 1 ? write data aah address 5555h read status register sr5 = 0 ? erase error write data aah address 5555h write data 55h address 2aaah byte/vpp=vih/vil write data 30h sector address operation done, device stays at read s.r. mode to continue other operations, do clear s.r. mode first
18 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* electrical specifications absolute maximum ratings rating value ambient operating temperature 0 c to 70 c storage temperature -65 c to 125 c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.6v vcc to ground potential -0.5v to 4.0v a9 -0.5v to 12.5v byte/vpp -0.5v to 11.5v notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 14 pf vin = 0v cout output capacitance 16 pf vout = 0v switching test circuits switching test waveforms 2.0v 0.8v 2.4v 0.45v test points input 1.5v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are < 5ns. device under test diodes = in3064 or equivalent cl = 35 pf including jig capacitance 6.2k 2.7k 3.3v cl ohm ohm
19 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* dc characteristics vcc = 3.3v 10% symbol parameter notes min. typ. max. units test conditions iil input load 1 1 ua vcc=vcc max current vin=vcc or gnd ilo output leakage 1 10 ua vcc=vcc max current vin=vcc or gnd isb1 vcc standby 1 20 50 ua vcc=vcc max current(cmos) ce=vcc 0.2v isb2 vcc standby 1 2 ma vcc=vcc max current(ttl) ce=vih icc1 vcc read 1 50 80 ma vcc=vcc max current f=10mhz, iout = 0 ma icc2 vcc program 1 15 30 ma program in progress current icc3 vcc erase current 1 15 30 ma erase in progress vil input low voltage 2 -0.3 0.6 v vih input high voltage 3 0.7xvcc vcc+0.3 v vol output low voltage 0.45 v iol=2.1ma, vcc =vcc min voh output high voltage 2.4 v ioh=-100ua, vcc=vcc min notes: 1. all currents are in rms unless otherwise noted. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. vil min. = -1.0v for pulse width is equal to or less than 50ns. vil min. = -2.0v for pulse width is equal to or less than 20ns. 3. vih max. = vcc + 1.5v for pulse width is equal to oe less than 20ns. if vih is over the specified maximum value, read operation cannot be guaranteed.
20 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* ac characteristics -- read operations 29l1611g-90 29l1611(g)-10 29l1611g-12 symbol descriptions min. max. min. max. min. max. unit conditions tacc address to output delay 90 100 120 ns ce=oe=vil tce ce to output delay 90 100 120 ns oe=vil toe oe to output delay 30 30 30 ns ce=vil tdf oe high to output delay 0 20 0 20 0 20 ns ce=vil toh address to output hold 0 0 0 ns ce=oe=vil tbacc byte to output delay 100 100 120 ns ce= oe=vil tbhz byte low to output in high z 20 20 20 ns ce=vil test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times: 5ns ? output load: 1ttl gate + 35pf(including scope and jig) ? reference levels for measuring timing: 1.5v note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
21 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 4.1 normal read timing waveforms addresses tacc tce tdf toh toe addresses stable data out valid vcc 3.3v gnd data out ce oe power-up standby device and address selection outputs enabled data valid standby power-down vcc vih vil vih vil vih vil voh vol high z high z vcc 1. for real world application, byte/vpp pin should be either static high(word mode) or static low(byte mode); dynamic switching of byte/vpp pin is not recommended. note: figure 4.2 page read timing waveforms valid address a3-a19 (a-1), a0~a2 ce oe data out tacc tpa tpa tpa toe toh tdf
22 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 5. byte timing waveforms addresses tacc tce tdf toh data output toe addresses stable data(q0-q7) ce oe byte/vpp vih vil vih vil vih vil vih vil voh vol voh vol high z high z data output data output high z tbacc high z tbhz data(q8-q15)
23 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* ac characteristics -- write/erase/program operations 29l1611g-90 29l1611(g)-10 29l1611g-12 symbol description min. max. min. max. min. max. unit twc write cycle time 90 100 120 ns tas address setup time 0 0 0 ns tah address hold time 60 60 60 ns tds data setup time 50 50 50 ns tdh data hold time 10 10 10 ns tces ce setup time 0 0 0 ns tghwl read recover timebefore write 0 0 0 twp write pulse width 60 60 60 ns twph write pulse width high 40 40 40 ns tbalc byte(word) address load cycle 0.3 30 0.3 30 0.3 30 us tbal byte(word) address load time 100 100 100 us tsra status register access time 120 120 120 ns tcesr ce setup before s.r. read 100 100 100 ns tvcs vcc setup time 2 2 2 us traw read operation set up time after write 20 20 20 ns tvps vpp setup time 2 2 2 us tvph vpp hold time 2 2 2 us
24 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 6. command write timing waveforms tas tds tah din tdh tghwl valid addresses oe data high z ce vcc byte/vpp twph twp twc tvcs 11v 1. byte/vpp pin should be static at 11v is equal to or less than during write operation. note: 2. byte/vpp pin should be static at ttl or cmos level during read operation.
25 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 7. automatic page program timing waveforms tas tds tah tdh tbalc a15~a19 ce oe data tvps twph twp 11v twc byte/vpp aah 55h a0h srd 55h 55h aah 2ah 55h 55h word offset address page address page address a6~a14 a0~a5 tbal tces traw tsra tvph write data last word offset address last write data
26 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 8. automatic sector/chip erase timing waveforms tas tds tah tdh a15~a19 ce oe data twph twp aah 55h 80h srd 5555h 2aaah 5555h sa/* twc a0~a14 tcesr tces tsra notes: 5555h 2aaah */5555h aah 55h 30h 1."*" means "don't care" in this diagram. 2."sa" means "sector adddress". 11v byte/vpp traw
27 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 9. sector protection algorithm start, plscnt=0 write data 60h address 5555h no write data 55h address 2aaah byte/vpp=vhh increment plscnt, to protect sector again yes yes no sr7 = 1 ? write data aah address 5555h read status register to verify protect status ? data = c2h ? write data aah address 5555h write data 55h address 2aaah write data 20h, sector address* byte/vpp=vih/vil verify protect status flow (figure 11) device failed yes no protect sector operation terminated sector protected,operation done, device stays at verify sector protect mode device stays at read s.r. mode yes plscnt = 25 ? no note : *only the top or the bottom sector address is vaild in this feature. i.e. sector address = (a19,a18,a17,a16,a15) = 00000b or 11111b
28 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 10. sector unprotect algorithm start, plscnt=0 write data 60h address 5555h no write data 55h address 2aaah byte/vpp=vhh increment plscnt, to unprotect sector again yes yes no sr7 = 1 ? write data aah address 5555h read status register to verify protect status ? data = 00h ? write data aah address 5555h write data 55h address 2aaah byte/vpp=vih/vil write data 40h, sector address* verify protect status flow (figure 11) device failed yes no unprotect sector operation terminated sector unprotected,operation done, device stays at verify sector protect mode device stays at read s.r. mode yes plscnt = 25 ? no note : *only the top or the bottom sector address is vaild in this feature. i.e. sector address = (a19,a18,a17,a16,a15) = 00000b or 11111b
29 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* figure 11. verify sector protect flow chart start byte/vpp=vih/vil write data 55h, address 2aaah byte/vpp=vhh write data aah, address 5555h write data 90h, address 5555h protect status read* * 1. protect status: data outputs c2h as protected sector verified code. data outputs 00h as unprotected sector verified code. 2. sepecified address will be either (a19,a18,a17,a16,a15,a1,a0) = (0000010) or (1111110), the rest of the address pins are don't care. 3. silicon id can be read via this flow chart. refer to table 4.
30 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* latchup characteristics min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 6.6v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.3v, one pin at a time. erase and programming performance(1) limits parameter min. typ.(2) max. units chip/sector erase time 200 1600 ms page programming time 5 150 ms chip programming time 80 240 sec erase/program cycles 100 cycles note: (1).sampled, not 100% tested. excludes external system level over head. (2).typing values are measured at 25 c, noninal voltage
31 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* order information plastic package part no. access time operating current standby current package (ns) max.(ma) max.(ua) mx29l1611gpc-90 90 80 20 42 pdip MX29L1611GPC-10 100 80 20 42 pdip mx29l1611gpc-12 120 80 20 42 pdip mx29l1611pc-90 90 80 20 42 pdip mx29l1611pc-10 100 80 20 42 pdip mx29l1611pc-12 120 80 20 42 pdip
32 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* package information 42-pin plastic dip(600 mil)
33 p/n:pm0604 rev. 0.8, jan. 24, 2002 mx29l1611g / mx29l1611* revision history revision description page date 0.2 erase/programming operation voltage change(10v-->11v) p1,4,9,14,25 mar/15/1999 p26,27 modify bus operation p5 modify command definitions p6 modify "automatic page program time waveforms" p26 modify "sector protection algorithm" p28 modify "sector unprotect algorithm" p29 modify "erase and programming performance" p31 0.3 description correction p1,6,7,9,13,19 mar/23/1999 p22,23 plug in byte/vpp operation description p15,16,17,18,28,29,30 0.4 delete page mode operation p1,9,20,22 may/07/1999 delete erase suspard/resume operation p6,10,12,16,17,19 modify description p1,2 undate erase and program performance p30 0.5 change fast random access time:100ns-->90ns p1 apr/07/2000 change 29l1611g-10-->29l1611g-90 p20 tacc:100-->90, tce:100-->90 change verify protect status flow(figure 12)-->(figure 11) p27,28 0.6 modify ac characteristics 29l1611g-10-->29l1611g-90 ; p23 apr/18/2000 twc:120-->90 p23 0.7 correct id binay code from 1000 to 0110 p8 jul/10/2001 modify package information p31 0.8 1.add page read 30ns p1 jan/24/2002 2.add page read p9 3.add 29l1611(g)-10 p20 4.add page read timing waveform p21 5.add 29l1611(g)-10 p23 6.add order information p31
mx29l1611g / mx29l1611* m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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